The invention relates to an integrating digital-to-analog converter (DAC), particularly for digital systems requiring a fast and accurate high resolution conversion of a digital input code into a corresponding analog output voltage.
An overwhelming majority of the conventional DACs comprises an analog switch matrix controlled by the digital input code, and an associated resistive network for obtaining binary weighted partial currents. These currents are added in a summing unit and possibly amplified so that a voltage proportional to the input code is provided. Generally, DACs with a current or voltage output can be distinguished.
These DACs require a high number of components. The values of the resistors must be accurately matched and also have a possibly identical temperature coefficient. The parasitic capacitances as well as switching delays of the analog switches cause high transient voltage spikes. Output amplifiers are employed as DACs with current output and often low output impedance dependent on input code, are of little use. The new error sources such as offset voltage, overshoot tendency and high settling time must be taken into account.
A simple conversion method is a DAC with a reverse counter and an integrator. The circuit contains also a single switch. The input code is loaded into the counter. The counting starts when the switch is turned on so that the output voltage of the integrator ramps up from ground potential. The switch is turned off when the counter reaches zero, whereby the integrator stores the conversion result.
This circuit offers a very high accuracy, high noise rejection, extremely low nonlinearities and high monotonicity. The circuit is also very simple. However, the DAC is extraordinary slow and for that reason practically meaningless.
The invention is intended to provide a DAC with all the above mentioned advantages as well as a very high speed. A DAC according to the present invention includes means for separating the digital input code into a plurality of groups of adjacent bits with each group having a separate weight, a separate counting means for counting thru each separate group of bits, an integrator means for integrating an input signal at a determinable rate and providing an integrated output signal in response thereto, and means for determining the rate of integration in response to the counting and to the weight of the counting means.